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cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05446 rev. *c revised june 04, 2007 cy62167ev30 mobl ? 16-mbit (1m x 16 / 2m x 8) static ram features ? tsop i package configurable as 1m x 16 or as 2m x 8 sram ? very high speed: 45 ns ? wide voltage range: 2.20v?3.60v ? ultra low standby power ? typical standby current: 1.5 a ? maximum standby current: 12 a ? ultra low active power ? typical active current: 2.2 ma @ f = 1 mhz ? easy memory expansion with ce 1 , ce 2 , and oe features ? automatic power down when deselected ? cmos for optimum speed/power ? offered in pb-free 48-ball bga and 48-pin tsop i packages functional description [1] the cy62167ev30 is a high performance cmos static ram organized as 1m words by 16 bits / 2m words by 8 bits. this device features advanced circuit design to provide an ultra low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption by 99% when addresses are not toggling. place the device into standby mode when deselected (ce 1 high or ce 2 low or both bhe and ble are high). the input and output pins (io 0 through io 15 ) are placed in a high-impedance state when: the device is deselected (ce 1 high or ce 2 low), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or a write operation is in progress (ce 1 low, ce 2 high and we low). to write to the device, take chip enables (ce 1 low and ce 2 high) and write enable (we ) input low. if byte low enable (ble ) is low, then data from io pins (io 0 through io 7 ) is written into the location specified on the address pins (a 0 through a 19 ). if byte high enable (bhe ) is low, then data from the io pins (io 8 through io 15 ) is written into the location specified on the address pins (a 0 through a 19 ). to read from the device, take chip enables (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on io 0 to io 7 . if byte high enable (bhe ) is low, then data from memory will appear on io 8 to io 15 . see the ?truth table? on page 10 for a complete description of read and write modes. logic block diagram 1m 16 / 2m x 8 ram array io 0 ?io 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 io 8 ?io 15 we ble bhe a 16 a 0 a 1 a 17 a 9 a 18 a 10 ce 2 ce 1 a 19 byte power down circuit bhe ble ce 2 ce 1 note 1. for best practice recommendations, refer to the cypress application note an1064, sram system guidelines . [+] feedback [+] feedback
document #: 38-05446 rev. *c page 2 of 13 cy62167ev30 mobl ? pin configuration [2, 3, 4] 48-ball fbga top view 48-pin tsop i top view product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1 mhz f = f max min typ [5] max typ [5] max typ [5] max typ [5] max cy62167ev30ll 2.20 3.0 3.60 45 2.2 4.0 25 30 1.5 12 we a 11 a 10 a 6 a 0 ce 1 io 10 io 8 io 9 a 4 a 5 io 11 io 13 io 12 io 14 io 15 v ss a 9 a 8 oe vss a 7 io 0 bhe ce 2 a 17 ble v cc io 2 io 1 io 3 io 4 io 5 io 6 io 7 a 15 a 14 a 13 a 12 a 19 a 18 nc 3 2 6 5 4 1 d e b a c f g h a 16 nc v cc a 1 a 2 a 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we ce 2 nc bhe ble a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte vss io15/a20 io7 io14 io6 io13 io5 io12 io4 vcc io11 io3 io10 io2 io9 io1 io8 io0 oe vss ce 1 a0 notes 2. nc pins are not connected on the die. 3. the byte pin in the 48-tsopi package has to be tied to v cc to use the device as a 1m x 16 sram. the 48-tsopi package can also be used as a 2m x 8 sram by tying the byte signal to v ss . in the 2m x 8 configuration, pin 45 is a20, while bhe , ble and io 8 to io 14 pins are not used. 4. ball h6 for the fbga package can be used to upgrade to a 32m density. 5. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc (typ), t a = 25c. [+] feedback [+] feedback
document #: 38-05446 rev. *c page 3 of 13 cy62167ev30 mobl ? maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ............. .............. ..... ?65c to + 150c ambient temperature with power applied........... .............. .............. ..... ?55c to + 125c supply voltage to ground potential ....................... ....... ?0.3v to 3.9v (v cc (max) + 0.3v dc voltage applied to outputs in high z state [6, 7] .............. ?0.3v to 3.9v (v cc (max) + 0.3v dc input voltage [6, 7] .......... ?0.3v to 3.9v (v cc (max) + 0.3v output current into outputs (low) ............................ 20 ma static discharge voltage......... ........... ............ ........... >2001v (mil-std-883, method 3015) latch up current...................................................... >200 ma operating range device range ambient temperature v cc [8] cy62167ev30ll industrial ?40c to +85c 2.2v to 3.6v electrical characteristics over the operating range parameter description test conditions 45 ns unit min typ [5] max v oh output high voltage 2.2 < v cc < 2.7 i oh = ?0.1 ma 2.0 v 2.7 < v cc < 3.6 i oh = ?1.0 ma 2.4 v v ol output low voltage 2.2 < v cc < 2.7 i ol = 0.1 ma 0.4 v 2.7 < v cc < 3.6 i ol = 2.1ma 0.4 v v ih input high voltage 2.2 < v cc < 2.7 1.8 v cc + 0.3v v 2.7 < v cc < 3.6 2.2 v cc + 0.3v v v il input low voltage 2.2 < v cc < 2.7 ?0.3 0.6 v 2.7 < v cc < 3.6 for fbga package ?0.3 0.8 v for tsop i package ?0.3 0.7 [9] v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc (max) i out = 0 ma cmos levels 25 30 ma f = 1 mhz 2.2 4.0 ma i sb1 automatic ce power down current?cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v v in > v cc ? 0.2v, v in < 0.2v, f = f max (address and data only), f = 0 (oe , we , bhe and ble ), v cc = 3.60v 1.5 12 a i sb2 [10] automatic ce power down current?cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.60v 1.5 12 a capacitance [11] parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf notes 6. v il (min) = ?2.0v for pulse durations less than 20 ns. 7. v ih (max) = v cc + 0.75v for pulse durations less than 20 ns. 8. full device ac operation assumes a 100 s ramp time from 0 to v cc (min) and 200 s wait time after v cc stabilization. 9. under dc conditions the device meets a v il of 0.8v. however, in dynamic conditions input low voltage applied to the device must not be higher than 0.7v. this is applicable to tsop i package only. 10. only chip enables (ce 1 and ce 2 ), byte enables (bhe and ble ) and byte need to be tied to cmos levels to meet the i sb2 / i ccdr spec. other inputs can be left floating. 11. tested initially and after any design or proce ss changes that may affect these parameters. [+] feedback [+] feedback
document #: 38-05446 rev. *c page 4 of 13 cy62167ev30 mobl ? thermal resistance [11] parameter description test conditions bga tsop i unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 55 60 c/w jc thermal resistance (junction to case) 16 4.3 c/w ac test loads and waveforms parameters 2.2v to 2.7v 2.7v to 3.6v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v data retention characteristics over the operating range parameter description conditions min typ [5] max unit v dr v cc for data retention 1.5 v i ccdr [10] data retention current v cc = 1.5v, ce 1 > v cc ? 0.2v, ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v 10 a t cdr [11] chip deselect to data retention time 0ns t r [12] operation recovery time t rc ns data retention waveform [13] v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thvenin equivalent all input pulses r th r1 v cc (min) v cc (min) t cdr v dr > 1.5 v data retention mode t r ce 1 or v cc bhe . ble ce 2 or notes 12. full device operation requires linear v cc ramp from v dr to v cc (min) > 100 s or stable at v cc (min) > 100 s. 13. bhe .ble is the and of both bhe and ble . chip can be deselected by eith er disabling the chip enable signals or by disabling both bhe and ble . [+] feedback [+] feedback
document #: 38-05446 rev. *c page 5 of 13 cy62167ev30 mobl ? switching characteristics over the operating range [14, 15] parameter description 45 ns unit min max read cycle t rc read cycle time 45 ns t aa address to data valid 45 ns t oha data hold from address change 10 ns t ace ce 1 low and ce 2 high to data valid 45 ns t doe oe low to data valid 22 ns t lzoe oe low to low z [16] 5ns t hzoe oe high to high z [16, 17] 18 ns t lzce ce 1 low and ce 2 high to low z [16] 10 ns t hzce ce 1 high and ce 2 low to high z [16, 17] 18 ns t pu ce 1 low and ce 2 high to power up 0 ns t pd ce 1 high and ce 2 low to power down 45 ns t dbe ble / bhe low to data valid 45 ns t lzbe ble / bhe low to low z [16] 10 ns t hzbe ble / bhe high to high z [16, 17] 18 ns write cycle [18] t wc write cycle time 45 ns t sce ce 1 low and ce 2 high to write end 35 ns t aw address setup to write end 35 ns t ha address hold from write end 0 ns t sa address setup to write start 0 ns t pwe we pulse width 35 ns t bw ble / bhe low to write end 35 ns t sd data setup to write end 25 ns t hd data hold from write end 0 ns t hzwe we low to high-z [16, 17] 18 ns t lzwe we high to low-z [16] 10 ns notes 14. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 1 v/ns, timing reference levels of v cc (typ)/2, input pulse levels of 0 to v cc (typ), and output loading of the specified i ol /i oh as shown in ?ac test loads and waveforms? on page 4 . 15. ac timing parameters are subject to byte enable signals (bhe or ble ) not switching when chip is disabled. see application note an13842 for further clarification. 16. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 17. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state. 18. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe or ble or both = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be refere nced to the edge of the signal that terminates the write. [+] feedback [+] feedback
document #: 38-05446 rev. *c page 6 of 13 cy62167ev30 mobl ? switching waveforms figure 1 shows address transition controlled read cycle waveforms. [19, 20] figure 1. read cycle no. 1 figure 2 shows oe controlled read cycle waveforms. [20, 21] figure 2. read cycle no. 2 previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzbe t lzbe t hzce t dbe oe ce 1 address ce 2 bhe /ble data out v cc supply current high i cc i sb impedance notes 19. the device is continuously selected. oe , ce 1 = v il , bhe , ble or both = v il , and ce 2 = v ih . 20. we is high for read cycle. 21. address valid before or similar to ce 1 , bhe , ble transition low and ce 2 transition high. [+] feedback [+] feedback
document #: 38-05446 rev. *c page 7 of 13 cy62167ev30 mobl ? figure 3 shows we controlled write cycle waveforms. [18, 22, 23] figure 3. write cycle no. 1 switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data t bw note 24 ce 1 address ce 2 we data io oe bhe /ble notes 22. data io is high impedance if oe = v ih . 23. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 24. during this period the ios are in output state. do not apply input signals. [+] feedback [+] feedback
document #: 38-05446 rev. *c page 8 of 13 cy62167ev30 mobl ? figure 4 shows ce 1 or ce 2 controlled write cycle waveforms. [18, 22, 23] figure 4. write cycle no. 2 figure 5 shows we controlled, oe low write cycle waveforms. [23] figure 5. write cycle no. 3 switching waveforms (continued) t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data t bw t sa note 24 ce 1 address ce 2 we data io oe bhe /ble valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 24 ce 1 address ce 2 we data io bhe /ble [+] feedback [+] feedback
document #: 38-05446 rev. *c page 9 of 13 cy62167ev30 mobl ? figure 6 shows bhe /ble controlled, oe low write cycle waveforms. [23] figure 6. write cycle no. 4 switching waveforms (continued) t hd t sd t sa t ha t aw t wc valid data t bw t sce t pwe note 24 ce 1 address ce 2 we data io bhe /ble [+] feedback [+] feedback
document #: 38-05446 rev. *c page 10 of 13 cy62167ev30 mobl ? truth table ce 1 ce 2 we oe bhe ble inputs/outputs mode power hxxxxxhigh z deselect/power-down standby (i sb ) xlxxxxhigh z deselect/power down standby (i sb ) xxxxhhhigh z deselect/power down standby (i sb ) lhhllldata out (io 0 ?io 15 ) read active (i cc ) lhhlhldata out (io 0 ?io 7 ); high z (io 8 ?io 15 ) read active (i cc ) lhhllhhigh z (io 0 ?io 7 ); data out (io 8 ?io 15 ) read active (i cc ) l h h h l h high z output disabled active (i cc ) lhhhhlhigh z output disabled active (i cc ) l h h h l l high z output disabled active (i cc ) l h l x l l data in (io 0 ?io 15 ) write active (i cc ) l h l x h l data in (io 0 ?io 7 ); high z (io 8 ?io 15 ) write active (i cc ) lhlxlhhigh z (io 0 ?io 7 ); data in (io 8 ?io 15 ) write active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 45 CY62167EV30LL-45BVXI 51-85150 48-ball fine pi tch ball grid array (pb-free) industrial cy62167ev30ll-45zxi 51-85183 48-pin tsop i (pb-free) [+] feedback [+] feedback
document #: 38-05446 rev. *c page 11 of 13 cy62167ev30 mobl ? package diagrams figure 7. 48-ball vfbga (6 x 8 x 1 mm), 51-85150 a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 51-85150-*d [+] feedback [+] feedback
document #: 38-05446 rev. *c page 12 of 13 cy62167ev30 mobl ? figure 8. 48-pin tsop i (12 mm x 18.4 mm x 1.0 mm), 51-85183 package diagrams (continued) 1 n 0.020[0.50] 0.007[0.17] 0.037[0.95] 0.002[0.05] 0-5 max. 0.028[0.70] 0.010[0.25] 0.004[0.10] 0.011[0.27] 0.041[1.05] 0.047[1.20] 0.472[12.00] 0.724 [18.40] 0.787[20.00] 0.006[0.15] typ. 0.020[0.50] 0.008[0.21] gauge plane seating plane 0.004[0.10] dimensions in inches[mm] min. max. jedec # mo-142 51-85183-*a [+] feedback [+] feedback
document #: 38-05446 rev. *c page 13 of 13 cy62167ev30 mobl ? document history page document title: cy62167ev30 mobl ? 16-mbit (1m x 16 / 2m x 8) static ram document number: 38-05446 rev. ecn no. issue date orig. of change description of change ** 202600 01/23/04 aju new data sheet *a 463674 see ecn nxr converted from advance information to preliminary removed ?l? bin and 35 ns speed bin from product offering modified data sheet to include x8 configurability. changed ball e3 in fbga pinout from dnu to nc changed the i sb2(typ) value from 1.3 a to 1.5 a changed the i cc(max) value from 40 ma to 25 ma changed vcc stabilization time in footnote #9 from 100 s to 200 s changed the ac test load capacitance value from 50 pf to 30 pf corrected typo in data retention characteristics (t r ) from 100 s to t rc ns changed t oha , t lzce , t lzbe , and t lzwe from 6 ns to 10 ns changed t lzoe from 3 ns to 5 ns. changed t hzoe , t hzce , t hzbe , and t hzwe from 15 ns to 18 ns changed t sce , t aw , and t bw from 40 ns to 35 ns changed t pe from 30 ns to 35 ns changed t sd from 20 ns to 25 ns updated 48 ball fbga package information. updated the ordering information table *b 469169 see ecn nsi minor change: moved to external web *c 1130323 see ecn vkn converted from preliminary to final changed i cc max spec from 2.8 ma to 4.0 ma for f=1mhz changed i cc typ spec from 22 ma to 25 ma for f=f max changed i cc max spec from 25 ma to 30 ma for f=f max added v il spec for tsop i package and footnote# 9 added footnote# 10 related to i sb2 and i ccdr changed i sb1 and i sb2 spec from 8.5 a to 12 a changed i ccdr spec from 8 a to 10 a added footnote# 15 related to ac timing parameters [+] feedback [+] feedback

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